The present invention relates generally to a press-connected type semiconductor device, and more particularly to a multi-chip press-connected type semiconductor device including a plurality of semiconductor chips.
An IGBT defined as a MOS gate drive type switching device is widely employed as one of semiconductor devices for power control, and an FRD (fast recovery diode) mix-mounted IGBT serving to make full use of the characteristic thereof is known as one example of a multi-chip press-connected type semiconductor device.
The multi-chip press-connected type semiconductor device is a semiconductor device contrived to improve a rated value in a way that establishes an inverse parallel connection between electrodes of both of an IGBT chip and a free wheel diode chip (or FRD chip) by applying a pressure to between electrode plates after disposing the IGBT chip and the FRD chip.
This type of semiconductor device is now described in detail. A chip frame composed of a synthetic resin is attached to respective terminal portions of a plurality of chips, and the chips are arrayed on the same plane so as to abut on this chip frame each other. A first electrode plate and a second electrode plate are disposed on both of surface sides thereof and press-fixed to an electrode of each chip by pressing the electrode plates against the chip, thereby establishing the electric connection with reduced loss.
FIG. 8 is a schematic diagram showing a layout of the chips disposed on a disk-shaped heat buffer plate 108 in the multi-chip press-connected type semiconductor device. Referring to FIG. 8, respective sections represent IGBT chips and FRD chips, and there is shown a state of being attached with a holder that will hereinafter be described.
The layout of the chips in the conventional device illustrated in FIG. 8 is that the IGBT chips and the FRD chips are so disposed that chips are dispersed to the greatest possible degree as to be accommodated within the disk-shaped heat buffer plate 108 for the purpose of taking an exothermic balance between the case of electrifying only the IGBT chips and the case of electrifying only the diode chips.
A numerical quantity and the layout of the IGBT chips and the FRD chips can be arbitrarily selected according to required rating, however, an allocation of the numerical quantity of the chips within one single device is set, wherein the number of the IGBT chips is normally larger than the number of the FRD chips in order to enhance a current cut-off capability as in the form of the device.
Herein, an IGBT device has twenty-one pieces of layout sections, wherein thirteen sections are given to the IGBT chips, and eight sections are given to the FRD chips. Chip layout positions are allocated such that the numbers are given sequentially from an upper left to the right side in FIG. 8, and, when reaching the right end, the subsequent numbers are given from the left end in the next row. In this example, the chip numbers 1, 3, 4, 6, 8, 9, 11, 13, 14, 16, 18, 19 and 21 represent totally thirteen pieces of IGBT chips, and the chip numbers 2, 5, 7, 10, 12, 15, 17 and 20 (indicated by hatching) represent totally eight pieces of FRD chips. It can be understood that the IGBT chip and the FRD chip are alternately arranged in each row when paying attention to every row-direction.
FIG. 9 is a sectional view taken along the line A–A′ in FIG. 8, showing a structure. The IGBT chips 101 and the FRD chips 102 are mounted respectively on separation type heat buffer plates 103. In this state, a collector electrode is provided on an upper surface of the IGBT chip 101, and a cathode electrode is provided on an upper surface of the FRD chip 102.
Further, a plastic holder 104 for acquiring a chip-to-chip withstand voltage is fitted into a side terminal portion of each chip, thereby positioning the chip in a normal position. Disposed under each heat buffer plate 103 is a lower electrode plate 105 including emitter electrode post portions 105A each assuming a protruded shape matching with the heat buffer plate 103. A gate substrate 106 for control voltage distribution to the gate electrode of the IGBT chip 101, is provided in a space between the emitter electrode post portions, and a resinous member 107 for fixing the chip is provided above the gate substrate 106. Note that an illustration of a connecting portion between the gate substrate 106 and a chip gate pad is omitted for simplicity in FIG. 9.
The heat buffer plate 108 and an upper electrode plate 109, which are composed of, e.g., molybdenum, are provided upwardly of the chips 101, 102. The heat buffer plate 108 abuts on the collector side of the IGBT chip 101 and on the cathode side of the FRD chip 102, thus connecting these chips in common.
Then, the upper electrode plate and the lower electrode plate are fastened by screws with a compression spring interposed therebetween. With this configuration, the electrodes of the respective chips are efficiently connected, and the heat radiation is efficiently conducted.
Incidentally, the related patent documents are given as follows:
Japanese Patent Publication No. 3256636
Japanese Patent Application Laid-Open Publication No. 2003-7968
As explained above, in the thus constructed press-connected type semiconductor device, the number of the IGBT chips is normally set larger than the number of the FRD chips in order to enhance the current cut-off capability as in the form of the device. Hence, as the number of the FRD chips in one single device is smaller than the number of the IGBT chips, in the case of making an electric current having the same magnitude conductive thereto, an exothermic quantity of the FRD chip is larger than an exothermic quantity of the IGBT chip. In terms of safety, however, it is difficult to reduce the numerical quantity of the IGBT chips because of a necessity for giving a sufficient margin to the current cut-off capacity assured by the semiconductor device. Consequently, there arises a problem in which a power capacity that can be handled by the semiconductor device is restricted mainly by a heat resistance of the FRD chip.